Author Description

SystemVerilog Assertions Handbook, 2nd Edition is an excellent reference for learning the basics of the assertion language. The book includes the new IEEE 1800 updates for assertions and for the checker. The new language updates are clearly tagged with sidebars. Syntax summaries along with side examples help in learning the syntax. There are many practical examples with graphical representations and simulation runs that demonstrate the concepts. Basic rules are listed, often with quotes from the standard, and then explained. The book goes beyond the standard to demonstrate many subtleties that produce unexpected results and poor performance, and flags the pitfalls to avoid. It is a great refresher for experienced users and for those looking to understand what is new in the SVA language for the IEEE release. The book presents formal verification along with the experience of two models formally verified with OneSpin 360TM Module Verifier. Additional chapters present methodology, guidelines, and application perspectives. All code examples are downloadable. This book is co-authored by: Ben Cohen, Srinivasan Venkataramanan, Ajeetha Kumari, and Lisa Piper