Author Description

Material from a May 2002 symposium describe recent work in processor pipelines, processor scheduling, safety and reliability, power aware architecture, memory systems, dynamic optimization, vector architectures, and supporting deep speculation. Some subjects include transient-fault recovery using simultaneous multithreading, power and performance evaluation of globally asynchronous locally synchronous processors, implementing optimizations at decode time, and managing multiconfiguration hardware via dynamic working set analysis. Other areas explored are speculative dynamic vectorization, design tradeoffs for the Alpha EV8 conditional branch predictor, difficult-path branch prediction using subordinate microthreads, and efficient dynamic scheduling through tag elimination. This work lacks a subject index. Annotation c. Book News, Inc., Portland, OR (booknews.com)