Author Description

A Digital Signal Processor with specific instruction sets and meant for a specific application is called as Application specific Instruction set Processor(ASIP). The optimization of an ASIP becomes handy if it is designed in a higher level of abstraction that is higher than Register Transfer Level (RTL). Several stages are required to design a processor which are architecture design implementation, software development, instruction and system verification. Verification of such ASIPs at various design stages is a tedious job to do. This book presents the architecture description of a simple DSP processor using Architecture Description Language (ADL) based instruction set description. The design process is more consistent after allowing maximum flexibility. Furthermore, it enables the design process in both instruction and cycle accurate modes. The design process of a three stage pipelined FIR Filter processor is demonstrated as a case study.