This book investigates the challenges and methodologies for detecting small delay defects in nanoscale CMOS integrated circuits. It addresses the increasing complexity of modern integrated circuits, where manufacturing variations and process fluctuations can lead to subtle timing errors that are difficult to identify using traditional testing methods. The work explores advanced test pattern generation techniques and fault modeling specifically designed to capture these elusive defects, aiming to improve the reliability and yield of nanoscale semiconductor devices.

This technical monograph is aimed at researchers and engineers in the field of semiconductor testing and design. Its focus on the specific challenges of nanoscale CMOS technology suggests a dense, specialized treatment of the subject matter. The detailed exploration of advanced techniques and fault modeling indicates a readership requiring a strong background in electrical engineering and integrated circuit design.