Author Description

Annotation This proceedings contains extended version of a selected subset of the contributions presented at the May 1999 IEEE workshop. The 27 papers share research and development (RandD) results in electronic testing. Topics include calculating efficient LFSR seeds for built-in self test, functional and structural testing of switched-current circuits, compaction of IDDQ test sequence using reassignment method, debug facilities in the TriMedia CPU64 architecture, deterministic BIST with partial scan, and using the BS register for capturing and storing n-bit sequences in real-time. Other papers address MEMs, switched capacitors, ATPG and fault modeling, fault simulation and fault coverage of analog circuits, FPGAs and regular arrays, and low power BIST. No subject index. Annotation copyrighted by Book News, Inc., Portland, OR.